Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction

The continued quest for finding a low-power and high-performance hardware algorithm signed number multiplication led to designing simple novel radix-8 multiplier with 3-bit grouping partial product reduction performed using magnitudes of the multiplicand multiplier. pre-computation stage constitutes magnitude calculation non-trivial computations required generate products. A new strategy is deployed in design improve speed low cost. 8×8, 16×16, 32×32, 64×64 designs are presented proposed architectures. Performance results include area, power, delay, power-delay-product synthesized post-layout 32 nm CMOS technology 1.05 V supply voltage.