SIMD Instruction-based Fast HEVC RExt Decoder
نویسندگان
چکیده
منابع مشابه
Implementation of fast HEVC encoder based on SIMD and data-level parallelism
This paper presents several optimization algorithms for a High Efficiency Video Coding (HEVC) encoder based on single instruction multiple data (SIMD) operations and data-level parallelism. Based on the analysis of the computational complexity of HEVC encoder, we found that interpolation filter, cost function, and transform take around 68% of the total computation, on average. In this paper, se...
متن کاملDecoder Hardware Architecture for HEVC
This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of steps in intra prediction and the introduction of a new in-loop filter. Several solutions to address ...
متن کاملAn improved hypothetical reference decoder for HEVC
Hypothetical Reference Decoder is a hypothetical decoder model that specifies constraints on the variability of conforming network abstraction layer unit streams or conforming byte streams that an encoding process may produce. High Efficiency Video Coding (HEVC) builds upon and improves the design of the generalized hypothetical reference decoder of H.264/ AVC. This paper describes some of the ...
متن کاملAn Asynchronous Instruction Length Decoder
This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium® Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II...
متن کاملHEVC Hardware Decoder Implementation for UHD Video Applications
In this paper, an efficient hardware architecture that exploits parallel processing for HEVC decoders is proposed by introducing (i) a Coding Tree Unit (CTU)-level pipelined architecture for single-core based processing; and (ii) a multi-core based parallel processing architecture for picture partition decoding with low latency while not requiring additional resources for in-loop filtering (ILF...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Journal of Broadcast Engineering
سال: 2015
ISSN: 1226-7953
DOI: 10.5909/jbe.2015.20.2.224