SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning
نویسندگان
چکیده
منابع مشابه
An iterative merging placement algorithm for the fixed-outline floorplanning
Given a set of rectangular modules with fixed area and variable dimensions, and a fixed rectangular circuit. The placement of Fixed-Outline Floorplanning with Soft Modules (FOFSM) aims to determine the dimensions and position of each module on the circuit. We present a two-stage Iterative Merging Placement (IMP) algorithm for the FOFSM with zero deadspace constraint. The first stage iteratively...
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-Fixed-outline floorplanning enables multilevel hierarchical design, where aspect ratios and area of floorplans are usually imposed by higher level floorplanning and must be satisfied. Simulated Annealing is widely used in the floorplanning problem. It is well-known that the solution space, solution perturbation, and objective function are very important for Simulated Annealing. In this paper, ...
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In this paper, we present DeFer—a fast, high-quality, scalable, and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a nonslicing floorplan by compacting a slicing floorplan. To find a good slicing floorplan, instead of searching through numerous slicing trees by simulated annealing as in traditional approaches, DeFer considers only one single slicing tree. However, we gener...
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Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show th...
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Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show th...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2013
ISSN: 0278-0070,1937-4151
DOI: 10.1109/tcad.2012.2228304