Research and design of digital unit for direct digital frequency synthesizer

Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA

This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...

Pentomics Patents: Direct Digital Frequency Synthesizer

Direct Digital Frequency Synthesizer Pentomics’ first DDS patent concerns a method and apparatus for DDS which, unlike the traditional table-lookup methods, uses a simplified “angle-rotation” algorithm implemented as a multiplierless feedforward datapath, allowing easy pipelining and limiting the accumulation of roundoff errors. Our DDS’s modular architecture permits outputs of arbitrary precis...

design and simulation of a modified 32-bit rom-based direct digital frequency synthesizer on fpga

this paper presents a modified 32-bit rom-based direct digital frequency synthesizer (ddfs). maximum output frequency of the ddfs is limited by the structure of the accumulator used in the ddfs architecture. the hierarchical pipeline accumulator (hpa) presented in this paper has less propagation delay time rather than the conventional structures. therefore, it results in both higher maximum ope...

An optimized Direct Digital Frequency Synthesizer (DDFS)

An optimized Direct Digital Frequency Synthesizer (DDFS) design in terms of reduced ROM, high throughput and speed is designed in this paper. DDFS is designed with 200 MHz reference clock frequency and 32 bit FTW for the generation of sine and cosine signal with 16 bit output frequency having frequency resolution of 0.0466 Hz and Phase resolution of 0.0055°. DDFS design is simulated using VHDL ...

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