Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
نویسندگان
چکیده
منابع مشابه
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
Two-step physical register deallocation (TSD) is an architectural scheme that enhances memory-level parallelism (MLP) by preexecuting instructions. Ideally, TSD allows exploitation of MLP under an unlimited number of physical registers, and consequently only a small register file is needed for MLP. In practice, however, the amount of MLP exploitable is limited, because there are cases where eit...
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ژورنال
عنوان ژورنال: IEICE Transactions on Information and Systems
سال: 2010
ISSN: 0916-8532,1745-1361
DOI: 10.1587/transinf.e93.d.3294