Processor architecture and data buffering

BASEL (Buffering Architecture SpEcification Language)

Buffering architectures and policies for their efficient management constitute one of the core ingredients of a network architecture. In this work we introduce a new specification language, BASEL, that allows to express virtual buffering architectures and management policies representing a variety of economic models. BASEL does not require the user to implement policies in a high-level language...

Counterrow Pipeline Processor Architecture Counterrow Pipeline Processor Architecture

The counter ow pipeline processor architecture (cfpp) is a proposal for a family of microarchitectures for risc processors. The architecture derives its name from its fundamental feature, namely that instructions and results ow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid p...

Stream Processor Architecture

Modular vector processor architecture targeting at data-level parallelism

Taking advantage of DLP (Data-Level Parallelism) is indispensable in most data streaming and multimedia applications. Several architectures have been proposed to improve both the performance and energy consumption for such applications. Superscalar and VLIW (Very Long Instruction Word) processors along with SIMD (Single-Instruction Multiple-Data) and vector processor (VP) accelerators, are amon...

The Superthreaded Processor Architecture

The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism available in general-purpose application programs. Unlike other C...