Pre-Emphasis Pulse Design for Random-Access Memory

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact process variation constant WL, cell current, resistance deciding path on optimum discussed. WL modeled fitting curves address accessed cell, which provides designers ability to set timing for BL (bit-line) operations, reducing average time.