منابع مشابه
Reduction of Clock Power in Sequential Circuits Using Multi-Bit Flip-Flops
Power reduction plays a vital role in VLSI design. Multi-bit flip-flop is an efficient method for clock power reduction. This method is to eliminate the redundant inverters by merging some flip-flops into multi-bit flip-flops. This multi-bit flip-flops can share the drive strength, dynamic power, area of the inverter chain and can even save the clock network power and facilitate the skew contro...
متن کاملConditional Techniques for Low Power Consumption Flip- Flops
Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve Energy-Delay Product for up to 14% for 50% input activity and save more than 50% in power consumption for quiet input. This property makes conditional methods suitable for high-performance VLSI systems.
متن کاملDesign of New Low Power –Area Efficient Static Flip-Flops
System on chip (SOC) design integrates many complex modules in one chip. As number of modules per chip is increasing, number of transistors in a chip increases resulting in increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. Flip-F...
متن کاملIndividual Flip-Flops with Gated Clocks for Low Power Datapaths
Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energyconsuming components of digital circuits. This paper presents techniques to reduce energy consu...
متن کاملDesign Of Low Power &Energy Proficient Pulse Triggered Flip- Flops
In this paper, pulse-triggered flip-flop types which are bidirectional elements in sequential logic circuits were designed. Initially, the pulse generation control logic is removed from the critical path to facilitate a faster discharge operation. Following low-power techniques are implemented, such as conditional capture, conditional precharge, conditional discharge, conditional data mapping, ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Research in Engineering and Technology
سال: 2014
ISSN: 2321-7308,2319-1163
DOI: 10.15623/ijret.2014.0314003