Phantom-GRAPE: Numerical software library to accelerate collisionless N-body simulation with SIMD instruction set on x86 architecture

ARM Instruction Set Simulation on Multi-Core x86 Hardware

Dynamic translation is a popular technique to build Instruction Set Simulators (ISS). The dynamic translation process must be fast or the translation overhead will outweigh the benefits of reusing code previously translated. In real hardware, decoding and execution are performed by separate units in parallel. With the arrival of multi-core x86 desktops, it is now possible to do translation and ...

Towards a Formalization of the X86 Instruction Set Architecture

We present a preliminary approach to defining a formal specification of the semantics of the X86 Instruction Set Architecture. The goal of the formalization is to support the dual requirements of analyzing the correctness of binaries executing on the architecture and investigating different safety and security properties of the architecture itself. In particular, we focus on the security proper...

An Instruction to Accelerate Software Caches

In this paper we propose an instruction to accelerate software caches. While DMAs are very efficient for predictable data sets that can be fetched before they are needed, they introduce a large latency overhead for computations with unpredictable access behavior. Software caches are advantageous when the data set is not predictable but exhibits locality. However, software caches also incur a la...

Instruction Set Architecture Abstraction

This technical report describes CHERI ISAv3, the third version of the This report describes the CHERI Instruction-Set Architecture (ISA) and design. The purpose of this tutorial was to introduce the computer architecture Pydgin is a framework for rapidly developing instruction-set simulators (ISSs) from a but is particularly well-suited for exploring the hardware/software abstraction. The Intel...

Q Instruction Set Architecture