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Many applications have stimulated the recent surge of interest single-chip parallel processing. In such machines, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it...
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ژورنال
عنوان ژورنال: Science
سال: 2009
ISSN: 0036-8075,1095-9203
DOI: 10.1126/science.326.5959.1460-d