Parallel Computation of CRC Using Special Generator Polynomials

Parallel Computation of Crc Using Special Generator Polynomials

CRC (Cyclic Redundancy Check) is an error detection method commonly used in data communication systems, computer networks and storage environments. In this method, the transmitter divides the message by an agreed upon polynomial called the generator and concatenates the calculated residue to the message. The properties of the generator determine the range of errors which are detectable in the r...

Parallel CRC Computation in FPGAs

This paper presents how to compute n-bit CRC checksums on FPGAs in parallel. For this task, a specialized logic minimization strategy is outlined. It achieves signiicantly better results than standard logic optimizers. For n 96, CRC designs with an n-bit I/O interface are poorly routable. However, for smaller I/O interfaces even a 128-bit CRC can be implemented.

Fast CRC Computation for Numeric Polynomials Using PCLMULQDQ Instruction

3 Executive Summary This paper presents a fast and efficient method of computing CRC on IA processors with generic polynomials using the carry-less multiplication instruction – PCLMULQDQ. Instead of reducing the entire message with traditional reduction algorithms, we use a faster folding approach to reduce an arbitrary length buffer to a small fixed size to be reduced further by traditional me...

An Optimal Software Framework for Parallel Computation of CRC

CRC is a common error detection method used in different areas such as information storage and data communication. CRC depends on modulo-2 division by a predetermined divisor called the generator. In this method, the transmitter divides the message by the generator and concatenates the calculated residue to the message. CRC is not able to detect every kind of errors. The properties of the gener...

Fast Parallel Computation of Polynomials Using Few Processes