Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations
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چکیده
منابع مشابه
Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations
The paper addresses some insights into the Euler path approach to find out the optimum gate ordering of CMOS logic gates. Minimization of circuit layout area is one of the fundamental considerations in circuit layout synthesis. Euler path approach suggests that finding a common Euler path in both the NMOS and PMOS minimizes the logic gate layout area. In this article, the minimization of layout...
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ژورنال
عنوان ژورنال: Journal of Computing and Information Technology
سال: 2007
ISSN: 1330-1136,1846-3908
DOI: 10.2498/cit.1000731