Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing secondary path in whole-chip electrostatic discharge (ESD) protection network. In this paper, ESD characteristics of traditional point TFET, line TFET Ge-source are investigated using technology computer-aided design (TCAD) simulations, an improved TFET-based scheme proposed. It found that has lower trigger voltage higher failure current compared to TFETs. However, network more vulnerable primary due low thermal instability. Simulation results show choosing proper germanium mole fraction source region can balance ability risk, consequently enhancing robustness.