Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

Computing-in-memory (CIM) is considered a feasible solution to the acceleration of multiply-accumulate (MAC) operations at low power. The key CIM parallel MAC in memory domain, and thus reductions power consumption memory-access latency. Resistive random access (RRAM) can be good candidate for given its data nonvolatility, high density, low-latency read-out, multilevel representation, inherent current accumulation capability. Particularly, last two attributes offer analog domain. However, fully operation scheme causes significant area overheads peripheral circuits, particularly, analog-to-digital converters. To compensate these downsides using digital processing, method sub-array-wise partial over weight-resistors that are optimally split minimize circuits proposed. simulations performed highlight optimal sub-array 4 × w / 2 size. That is, weight-splitting such single w-bit weight represented by RRAM cells, i.e., 2-bit each cell. For 8-bit weights, figure merit (FOM) this case reaches ≈28.3 FOM no weight-splitting.