Optimal partitioners and end-case placers for standard-cell layout

Optimal End-Case Partitioners and Placers for Standard-Cell Layout

We develop new optimal partitioning and placement codes for end-case processing in top-down standard-cell placement. Such codes are based on either enumeration or branch-and-bound, and are invoked for instances below prescribed size thresholds (e.g., < 30 cells for partitioning, or < 10 cells for placement). Our optimal partitioners handle tight balance constraints and uneven cell sizes transpa...

Optimal decoupling capacitor sizing and placement for standard-cell layout designs

With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The ad...

a benchmarking approach to optimal asset allocation for insurers and pension funds

uncertainty in the financial market will be driven by underlying brownian motions, while the assets are assumed to be general stochastic processes adapted to the filtration of the brownian motions. the goal of this study is to calculate the accumulated wealth in order to optimize the expected terminal value using a suitable utility function. this thesis introduced the lim-wong’s benchmark fun...

Yield-Optimal Cell Layout Synthesis for CMOS Logic Cells

The recent improvement of VLSI process technologies enables us to integrate a large number of transistors on one chip, and significantly improves the circuit performance. On the other hand, the methodology of VLSI design becomes more and more complex and some new problems, such as Design For Manufacturability (DFM) have arisen. Due to the very high costs associated with the manufacturability of...

ACO for Optimal Sensor Layout