Novel Radiation-Hardened Latch Design for Space-Radiation Environments

A novel radiation hardened by design latch ∗

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the pr...

Technology Developments in Radiation - Hardened Electronics for Space Environments

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve ra...

Design Techniques for Radiation-Hardened FPGAs

With the RH1280 and RH1020, Actel Corporation introduces radiation-hardened versions of the popular A1280 and A1020 field programmable gate array (FPGA) familes with equivalent gate densities of 8,000 and 2,000 gate array gates, respectively. These products are processed to the QML process flow as defined in MIL-PRF-38535. They are manufactured with a 0.8 micron, two-level metal epitaxial bulk ...

Low cost and highly reliable radiation hardened latch design in 65 nm

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when pa...