Multi‐Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number high-impedance nodes, frequency compensation has biggest challenge in design multistage amplifiers. The new technique this study uses two differential stages to organize feedforward feedback paths. Five Miller loops a 500-pF load capacitor are driven by just tiny compensating capacitors, each with capacitance less than 10 pF. symbolic transfer function is calculated estimate circuit dynamics HSPICE TSMC 0.18 μm. CMOS technology used simulate proposed five-stage amplifier. A straightforward iterative approach also optimize parameters given known cost function. According simulation mathematical results, structure DC gain 190 dB, bandwidth product 15 MHz, phase margin 89°, power dissipation 590 μW.