Multiple-valued signed digit adder using negative differential resistance devices
نویسندگان
چکیده
منابع مشابه
Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated ...
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This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6m CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differential-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current...
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Quantum electronic devices with negative differential resistance (NDR) characteristics have been used to design compact multiplexers. These multiplexers may be used either as analog multiplexers where the signal on a single select line selects one out of four analog inputs, or as four-valued logic multiplexers where the select line and the input lines represent one of four quantized signal valu...
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Signed digit number systems provide the possibility of constant-time addition, where inter-digit carry propagation is eliminated. Carry-free addition for signed digit number systems is primarily a three-step process. However, the special case of maximally redundant signed digit number systems leads to more efficient carry-free addition. This has been previously achieved by speculative computati...
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Signed digit (SD) number systems support digit-parallel carry-free addition, where the sum digits absorb the possible signed carries in { 1,0,1}. Radix-2 maximally redundant SD (MRSD) number systems are particularly attractive. The reason is that, with the minimal (h + 1) bits per SD, maximum range is achieved. There are speculative MRSD adders that trade increased area and power for higher spe...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 1998
ISSN: 0018-9340
DOI: 10.1109/12.713314