MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines

Asynchronous Wave Pipelines for High Throughput Datapaths

A novel VLSI pipeline architecture for high-speed clockless computation is proposed. It features gate-level pipelining to maximize throughput and uses dynamic latches to keep the latency low. The most salient property is the asynchronous operation using a modi ed handshake protocol. Data words are accompanied by associated control signals resembling a local clock and propagate in coherent waves...

High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths

This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dualrail as well as single-rail. The new pipelines are latchfree and therefore are particularly well-suited for fine-grain pipelining, i.e., where each pipeline stage is only a single gate deep. The pipelines employ new control structures...

High Speed Power Efficient Asynchronous Adders

Performance Comparison of Clocked and Asynchronous Pipelines

Clock (synchronous) and self-timed (asynchronous) represent the two principal methodologies associated with timing control and synchronization of digital systems. In this paper, clocked and the asynchronous instruction and arithmetic pipelines are modeled and compared. The approach, which yields the best performance is dependent on technology parameters, operating range and pipeline algorithm c...

Leakage Power Reduction of Asynchronous Pipelines

With CMOS technology scaling, leakage power is expected to become a significant portion of the total power. Dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications. This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Quasi Delay Insens...