Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators

Specialized accelerators deliver orders of a magnitude higher performance than general-purpose processors. The ever-changing nature modern workloads is pushing the adoption Field Programmable Gate Arrays (FPGAs) as substrate choice. However, FPGAs are hard to program directly using Hardware Description Languages (HDLs). Even high-level HDLs, e.g., Spatial and Chisel, still require hardware expertise. This article adopts functional programming concepts provide hardware-agnostic higher-level abstraction. During synthesis, these abstractions mechanically lowered into Intermediate Representation (IR) that defines specific design point. novel IR expresses different forms parallelism standard memory features such asynchronous off-chip memories or synchronous on-chip buffers. Exposing at level essential for achieving high performance. viability this approach demonstrated on two stencil computations by exploring optimization space matrix-matrix multiplication. Starting from representation algorithms, our compiler produces low-level VHSIC Language (VHDL) code automatically. Several points evaluated an Intel Arria 10 FPGA, demonstrating ability exploit features. also shows designs produced competitive with highly tuned OpenCL implementations outperform code.