Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling
نویسندگان
چکیده
In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even 5 nm, has good properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) ~45 mV/V, and switching (ION/IOFF) ~106 shows a higher level electrostatic integrity. At LG optimized spacer dielectric exhibits ~5 orders improvement in IOFF is less than ~2 20 LG. Thus, from result analysis, dielectrics essential lower for better performance. For continued scaling, HfO2 ensures high lowest downfall ION 11.24% decline 15.8% 13.26% no Si3N4 respectively. With SiO2, Si3N4, spacers an which permissible ITRS low power requirements. Moreover, to flexibility towards analog/RF applications parameters transconductance (gm), generation factor (TGF), total capacitance (Cgg), cutoff frequency (fT) also determined. Furthermore, impact on dynamic (DP) static (SP) consumption presented. The findings show that JL NW one potential candidates future technology nodes.
منابع مشابه
An Extensive Evaluation of Futuristic Gate All Around Junctionless Nanowire MOSFET Using Numerical Simulation
This paper present an extensive review of homogeneously doped Junctionless Cylindrical Gate All Around (JL-CGAA) MOSFET using numerical simulations to look into deep physical insight of the device. The electrical and analog/RF performance has been investigated. The JL-C-GAA FET is more immune to short channel effect than the devices having p-n junctions. It also offers steeper subthreshold slop...
متن کاملInvestigation of Strain Profile Optimization in Gate-All-Around Suspended Silicon Nanowire FET
In this paper, we investigate the optimization of tensile strain caused by thermal oxidation in a doubly-clamped silicon nanowire FET to enhance the mobility of its carriers. Spacer technology combined with sacrificial oxidations was used to fabricate ≈ 100 nm wide nanowires. The temperature and the duration of sacrificial wet oxidation are the main parameters that determine the induced strain....
متن کاملLow-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique
In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al.
متن کاملPerformance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor
In this paper, we have presented a heterojunction gate all around nanowiretunneling field effect transistor (GAA NW TFET) and have explained its characteristicsin details. The proposed device has been structured using Germanium for source regionand Silicon for channel and drain regions. Kane's band-to-band tunneling model hasbeen used to account for the amount of band-to...
متن کاملRepresentation of the temperature nano-sensors via cylindrical gate-all-around Si-NW-FET
In this paper, the temperature dependence of some characteristics of cylindrical gate-all-around Si nanowire field effect transistor (GAA-Si-NWFET) is investigated to representing the temperature nano-sensor structures and improving their performance. Firstly, we calculate the temperature sensitivity of drain-source current versus the gate-source voltage of GAA-Si-NWFET to propose the temperatu...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Silicon
سال: 2021
ISSN: ['1876-9918', '1876-990X']
DOI: https://doi.org/10.1007/s12633-021-01471-z