Investigating memory prefetcher performance over parallel applications: From real to simulated

Memory prefetcher algorithms are widely used in processors to mitigate the performance gap between and memory subsystem. The complexities behind architectures algorithms, however, not only hinder development of accurate architecture simulators, but also understanding prefetcher's contribution performance, on both a real hardware simulated environment. In this paper, we contribute shed light role parallel High-Performance Computing applications, considering offered by simulators. We performed careful experimental investigation, executing NAS benchmark (NPB) Skylake machine, as well environment with ZSim Sniper taking into account Our results show that: (i) prefetching from L3 L2 cache presents better gains, (ii) contention execution constrains effect, (iii) Skylake's is poorly Sniper, (iv) noninclusive hinders simulation NPB Sniper's prefetchers.