Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET

The interface trap charges (ITC) associated reliability analysis of a charge-plasma based asymmetric double-gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high-κ gate dielectric (HJADGDLTFET) has been studied. HJADGDLTFET uses silicon at the drain channel region, germanium source which enhances band-to-band tunnelling source-channel junction, hence drive current is increased by one order concerning ADGDLTFET. Also, ADG (HfO2) have used to maintain low off-state values. primary intention this work investigate impact ITC for compare it ADGDLTFET considering DC, analog/RF, linearity parameters such as transfer characteristics, electric-field, electric potential, first-, second-, third-order transconductances (gm1, gm2, gm3), gate-to-drain capacitance (Cgd), cut-off frequency (fT), gain–bandwidth product, device efficiency, second- voltage intercept points (VIP2, VIP3), input (IIP3), intermodulation distortion. ATLAS simulation results show that more immune variation than conventional different polarities available semiconductor-oxide interface.