Instruction mapping techniques for processors with very long instruction word architectures

Abstract This paper presents an instruction mapping technique for generating a low-level assembly code digital signal processing algorithms. helps developers to implement retargetable kernel functions with the performance benefits of languages. The approach is aimed at exceptionally long word (VLIW) architectures, which most from proposed method. Mapped algorithms are described by signal-flow graphs, used find possible parallel operations. algorithm converted into and mapped target architecture. process also introduces optimization priority, leads more effective code. was verified on selected kernels, compared common programming methods, proved that it suitable VLIW architectures portability other systems.