Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures

Background: This paper presents an efficient two-dimensional (2-D) finite impulse response (FIR) filter using block processing for two different symmetries. Architectures a general (without symmetry) and symmetrical filters (diagonal quadrantal are implemented. The proposed architectures need fewer multipliers because of the symmetry coefficients. Methods: A distributed arithmetic (DA)- based multiplication method is used in architecture. A dual-port memory-based lookup table (DP-MLUT) instead lookup-table (LUT) to reduce area power FIR filter. filter's throughput increased by processing. Memory reuse memory sharing methods introduced, which reduces many registers hence circuit complexity. written Verilog Hardware Description Language synthesized Genus Synthesis tool-19.1 45nm technology with generic library Cadence vendor constraints. synthesis tool generates area, delay, reports. Power consumption calculated image size 64 X at 20 MHz frequency. Results: Compared existing architectures, results show improvements power, delay product (ADP), (PDP). MLUT-based 2-D Quadrantal Symmetry Filter (QSF) length 8 4 consumes 58.94% less occupies 59.5% 48.44% ADP 47.78% PDP compared best methods. Conclusions: novel DA-based architecture various symmetries realized. incorporated into coefficients minimize number multipliers. LUT optimized odd multiples or even storage techniques. Also, overall decreased DP-LUT-based area-power-efficient. It suited applications that have fixed coefficients.