Impact of Dimensions and Doping on the Breakdown Voltage of a Trench 4H-SiC Vertical JFET

In this paper we study the feasibility of design/fabrication a vertical trench 4H-SiC Junction Field Effect Transistor (JFET), assuming realistic constraints depth P+ implantation. The doping profile is obtained using Monte Carlo implantation simulation. calculation used drift-diffusion approach. JFET aims to achieve threshold voltage of-3V. We found that constraint in concomitance with proposed structure limits breakdown approximately 200V. This result premature induced by short channel effects, namely Drain Induced Barrier Lowering (DIBL). However, negative increase gate bias represses effect and improves roughly 1800V. At bias, reaching critical field strength at P+/N junction, which causes avalanche generation carriers. addition, have calculated dependence on drift pillar width. work also shows vulnerability design random fluctuation profile.