Histogram Computation with a Reconfigurable Memory Based Fast VLSI Architecture

نویسندگان

چکیده

Computation of histogram is the primary work that used in digital image processing systems. Mutual Information best measurement also for registration. Calculation mutual information requires obtaining separate and combining two images. By increase size, demand hardware resource computation increased. This paper about memory-based VLSI architecture has been shown. The existed by using plotting field programmable array. Parallelization functions a major problem due to memory collisions. So, avoid these collisions there new technique called parallel used. To implement histogram, it requiring dual–ported memory. making fast, are several benefits obtained. Some examples texture classification, compression, etc shown this manuscript.

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Implementation of VlSI Based Image Compression Approach on Reconfigurable Computing System - A Survey

Image data require huge amounts of disk space and large bandwidths for transmission. Hence, imagecompression is necessary to reduce the amount of data required to represent a digital image. Thereforean efficient technique for image compression is highly pushed to demand. Although, lots of compressiontechniques are available, but the technique which is faster, memory efficient and simple, surely...

متن کامل

Reconfigurable VLSI Architecture for FFT Processor

This paper presents a reusable intellectual property (IP) Coordinate Rotation Digital Computer (CORDIC)-based split-radix fast Fourier transform (FFT) core for orthogonal frequency division multiplexer (OFDM) systems, for example, Ultra Wide Band (UWB), Asymmetric Digital Subscriber Line (ADSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting – Terrestrial (DVB-T), Very High Bitrat...

متن کامل

VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware

A novel hardware architecture for memetic vector quantizer (VQ) design is presented in this paper. The architecture uses steady-state genetic algorithm (GA) for global search, and C-means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state GA operations. It also uses a pipeline architecture for the hardware...

متن کامل

DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture

This paper presents a novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC2) concept based on memory architecture for data-intensive (imaging, ...) and secure (cryptography, ...) applications. The proposed computing circuit is based on a 10-Transistor (10T) 3-Port SRAM bitcell array driven by a peripheral circuitry enabling all basic operations that can be traditionally ...

متن کامل

implementation of vlsi based image compression approach on reconfigurable computing system - a survey

image data require huge amounts of disk space and large bandwidths for transmission. hence, imagecompression is necessary to reduce the amount of data required to represent a digital image. thereforean efficient technique for image compression is highly pushed to demand. although, lots of compressiontechniques are available, but the technique which is faster, memory efficient and simple, surely...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Advances in transdisciplinary engineering

سال: 2022

ISSN: ['2352-751X', '2352-7528']

DOI: https://doi.org/10.3233/atde220805