High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process—Part II: Application to 3D Ultrathin Stacked-Die Chip Scale Packages

In the present study, the direct concentration approach (DCA) and the whole-field vapor pressure model developed in Part I of this work (Xie et al., 2009 “Direct Concentration Approach of Moisture Diffusion and Whole Field Vapor Pressure Modeling for Reflow Process: Part I–Theory and Numerical Implementation,” ASME J. Electron. Packag., 131, p. 031010) is applied to 3D ultrathin stacked-die chi...

Encapsulation Technology for 3 D Stacked Packages

The continuing demand for yet smaller and lighter electronic devices requires micro packaging where shrinkage in the geometry of the substrates as well as decrease of the area of the die is needed. Higher device and circuitry integration of the silicon die, finer pitch of fully populated arrays interconnections are examples of how the industry is meeting these miniaturizations demand. Today tec...

All-copper Chip-to-substrate Interconnections for Flip-chip Packages

Moisture absorption and desorption in wafer level chip scale packages

Article history: Received 28 May 2015 Received in revised form 18 June 2015 Accepted 29 June 2015 Available online xxxx

Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages

Detailed three-dimensional finite element analysis was carried out for area-array solder-bumped flip-chip packages. The analysis enabled determinations of accurate three-dimensional effects on stress distributions as well as local fracture behaviors under thermal load. The 3D analysis also estimated thermal fatigue life of solder bumps. Since dimensions of various components span more than thre...