High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits/3 Bits
نویسندگان
چکیده
منابع مشابه
A Novel High-speed Adder-Subtractor Design based on CNFET
Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometrydependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Presented design uses fourteen transistors, ten for full ...
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ژورنال
عنوان ژورنال: IEEJ Transactions on Electronics, Information and Systems
سال: 2001
ISSN: 0385-4221,1348-8155
DOI: 10.1541/ieejeiss1987.121.4_733