High Speed Area Efficient 32 Bit Wallace Tree Multiplier
نویسندگان
چکیده
منابع مشابه
Design of High Speed Hardware Efficient 4-bit Sfq Multiplier
A 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. The circuit area of the multiplier designed with the Booth encoder method is compared to that ...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2015
ISSN: 0975-8887
DOI: 10.5120/ijca2015905742