High Speed 32-bit Vedic Multiplier for DSP Applications
نویسندگان
چکیده
منابع مشابه
Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique for arithmetic computations based on 16 Sutras (Formulae). Transistor level implementation (ASIC) of Vedic Mathematics based 32-bit multiplier for high speed low power processor is reported in this paper. Simple Boolean logic is combined with ‘Vedic’ formulas, which reduces the partial products and s...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2016
ISSN: 0975-8887
DOI: 10.5120/ijca2016908478