High-Performance Top-Gated and Double-Gated Oxide–Semiconductor Ferroelectric Field-Effect Transistor Enabled by Channel Defect Self-Compensation Effect

In this article, we demonstrate a low-thermal budget defect-engineered process to achieve top-gated (TG) oxide–semiconductor ferroelectric field-effect transistors (FeFETs). The demonstrated TG FeFETs, with the channel length scaled down 40 nm, exhibit highly stabilized memory window (MW) of 2 V and high current ON/ OFF ratio $10^{{6}}$ . This is achieved by an engineered InGaZnOx (IGZO) InSnOx (ITO) heterojunction that produces defect self-compensation effect passivate intrinsic oxygen-deficient defects, existing in indium-gallium-zinc-oxide interface bulk. Effective interface/bulk defects passivation good control defect-induced carrier concentration has been notoriously difficult achieve. Hence, realizing performant oxide-based FeFETs back-end-of-line (BEOL) thermal constraints remains fundamental challenge. Our study shows engineering on FETs can be reliable solution overcome With such technique, now enable double-gated (DG) ITO–IGZO FeFET FETs. Such devices BEOL-compatible reconfigurable nonvolatile logic switches provide extremely low off-state leakage, switch conductance ratio, read-write disturb-free features.