High-performance carry chains for FPGA's
نویسندگان
چکیده
منابع مشابه
Generating high-performance arithmetic operators for FPGAs
This article addresses the development of complex, heavily parameterized and flexible operators to be used in FPGA-based floating-point accelerators. Languages such as VHDL or Verilog are not ideally suited for this task. The main problem is the automation of problems such as parameterdirected or target-directed architectural optimization, pipeline optimization, and generation of relevant test ...
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In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use...
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Adders are some of the most critical data path circuits requiring considerable design effort in order to “squeeze” out as much performance gain as possible. Many adder designs manage high performance by reducing the delay of the critical path, an effort that results in high area overhead in most cases. In this paper we present a carry lookahead adder (CLA) with a prediction scheme that results ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2000
ISSN: 1063-8210,1557-9999
DOI: 10.1109/92.831434