Hierarchical whitespace allocation in top-down placement
نویسندگان
چکیده
منابع مشابه
Hierarchical Whitespace Allocation in Top - Down Placement
Increased transistor density in modern commercial ICs typically originates in new manufacturing and defect prevention technologies [15], [16]. Additionally, better utilization of such low-level transistor density may result from improved software that makes fewer assumptions about physical layout in order to reliably automate the design process. In particular, recent layouts tend to have large ...
متن کاملHierarchical whitespace allocation in top-down placement
Increased transistor density in modern commercial ICs typically originates in new manufacturing and defect prevention technologies [15], [16]. Additionally, better utilization of such low-level transistor density may result from improved software that makes fewer assumptions about physical layout in order to reliably automate the design process. In particular, recent layouts tend to have large ...
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In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations. To this end, layout ...
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Recent work of Simon and Teng [17] observes that the recursive bisection (i.e., bipartitioning with equal partition target areas, and minimum possible allowed deviation from targets) heuristic for kway minimum-cut graph partitioning can have unbounded error, but that relaxing the balance constraints in each call to the bipartitioning engine can result in k-way net cuts within a small (O(logk)) ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2003
ISSN: 0278-0070
DOI: 10.1109/tcad.2003.818375