Formalizing Memory Accesses and Interrupts

Formalizing Memory Accesses and Interrupts

The hardware/software boundary in modern heterogeneous multicore computers is increasingly complex, and diverse across different platforms. A single memory access by a core or DMA engine traverses multiple hardware translation and caching steps, and the destination memory cell or register often appears at different physical addresses for different cores. Interrupts pass through a complex topolo...

Behavioural types for non-uniform memory accesses

Concurrent programs executing on NUMA architectures consist of concurrent entities (e.g. threads, actors) and data placed on different nodes. Execution of these concurrent entities often reads or updates states from remote nodes. The performance of such systems depends on the extent to which the concurrent entities can be executing in parallel, and on the amount of the remote reads and writes. ...

Analyzing Memory Accesses in x86 Binary Executables

Response time distribution of flash memory accesses

Flash memory is becoming an increasingly important storage component among non-volatile storage devices. Its cost is decreasing dramatically, which makes it a serious competitor of disks and a candidate for enterprise-tier storage device of the future. Consequently, there is an urgent need for models and tools to analyse its behaviour and evaluate its effects on a system’s performance. We propo...

Analyzing Memory Accesses in Obfuscated x86 Executables

Programmers obfuscate their code to defeat manual or automated analysis. Obfuscations are often used to hide malicious behavior. In particular, malicious programs employ obfuscations of stack-based instructions, such as call and return instructions, to prevent an analyzer from determining which system functions it calls. Instead of using these instructions directly, a combination of other instr...