Failure-tolerant synchronous and self-timed circuits comparison

The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous traditionally use 2-of-3 voting principle ensure single failure, resulting in three times hardware costs. In ST circuits, due dual-rail signal coding two-phase control, even duplication provides a error tolerance level 2.1 3.5 higher than triple modular redundant counterpart. development new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for electronic circuits’ tolerance.