Fail-stop processors

Fail-Stop Signatures

Fail-stop signatures can briefly be characterized as digital signatures that allow the signer to prove that a given forged signature is indeed a forgery. After such a proof has been published, the system can be stopped. This type of security is strictly stronger than that achievable with ordinary digital signatures as introduced by Diffie and Hellman in 1976 and formally defined by Goldwasser, ...

Fail-Stop Signatures Without Trees

We construct the first fail-stop signature scheme where neither the signature length nor the length of the public key grows as a function of the number of messages that can be signed with one key. The computation needed for signing and testing is reduced similarly. This removes one of the main differences between the complexity of ordinary signature schemes and previous fail-stop signature sche...

The Fail-Stop Processor Approach*

The Fail-Stop Controller AE11

This work was supported by the JESSI project AE11. Abstract Using on-chip fault detection measures the Fail-Stop Controller AE11 was developed for safety critical applications aiming at high volume production of automotive and railway electronics. The trade-off between high defect coverage, short reaction time to faults and low chip area overhead results in a combination of Concurrent Checking,...

Factorization-Based Fail-Stop Signatures Revisited

Fail-stop signature (FSS) schemes are important primitives because in a fail-stop signature scheme the signer is protected against unlimited powerful adversaries as follows: Even if an adversary breaks the scheme’s underlying computational hard problem and hence forges a signature, then with overwhelming probability the signer is able to prove that a forgery has occurred (i.e. that the underlyi...