Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

In this article, authors explore radiation hardening techniques through the design of a test chip implemented in 16-nm FinFET technology, along with architectural and redundancy space exploration its modules. Nine variants matrix multiplication were taped out irradiated neutrons. The results obtained from neutron campaign revealed that radiation-hardened present superior resiliency when either local or global triple modular (TMR) schemes are employed. Furthermore, simulation-based fault injection was utilized to validate measurements effects different implementation strategies on failure rates. We further show interplay between these is not trivial capture synthesis optimizations can effectively break assumptions about effectiveness schemes.