Enhancing TCP via Hysteresis Switching: Theoretical Analysis and Empirical Evaluation

In this paper we study the relationship between TCP packet loss cycle and performance of time-sensitive traffic in data centers. Using real measurements analysis, find that such cycles are not long enough to enable most partition-aggregate applications recover their losses via 3-dup ACKs mechanism. As a result, Timeout (RTO) mechanism is frequently triggered, leading expansion flow completion times (FCT) by orders magnitude. Hence, seek an alternative method does change virtual machines can effectively expand duration short flows finish transfer without incurring cost RTO. To end, propose novel TCP-AQM alternates slow constant bitrate (CBR) mode fast rate hysteresis switching cycle. We prove stability proposed control theoretic model, then evaluate its gains small large scale NS2 simulation FPGA implementation prototype on NetFPGA platform. The results show considerable improvements FCT distribution reduction missed deadlines experiments.