Efficient FFT Computation in IFDMA Transceivers

Interleaved Frequency Division Multiple Access (IFDMA) has the salient advantage of lower Peak-to-Average Power Ratio (PAPR) than its competitors like Orthogonal FDMA (OFDMA). A recent research effort ours put forth a new IFDMA transceiver design significantly less complex conventional transceivers. The reduces complexity by exploiting certain correspondence between signal processing and Cooley-Tukey IFFT/FFT algorithmic structure so that streams can be inserted/extracted at different stages an module according to sizes streams. Although our prior work laid down theoretical foundation for transceiver’s structure, practical realization on specific hardware with resource constraints not been carefully investigated. This paper is attempt fill gap. Specifically, this puts heuristic algorithm called multi-priority scheduling (MPS) schedule execution butterfly computations in constraint limited number processors. resulting FFT computation, referred as MPS-FFT, much computation time when applied processing. Importantly, we derive bound optimal benchmark MPS-FFT. Our experimental results indicate processors power two: 1) MPS-FFT near-optimal time; 2) incurs 44.13% pipelined FFT.