Drain-Engineered Reconfigurable Transistor Exhibiting Complementary Operation

In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability realizes both nFET pFET electrical characteristics when adequately biased. The use of will significantly reduce the count in realizing sequential combinational circuits result highly compact design. uses dual fin structure having single mid-gap workfunction gate ( $\sim $ 4.65 eV) alongside metal (metal-silicide) drain regions. It employs n+/p+-i junctions at source-channel interface along with Schottky channel-drain interface. practice, metal-silicides such as erbium/ytterbium silicide (ErSix/YbSix) for n-drain platinum (PtSi) p-drain can be used they provide smallest electron hole Schottky-barrier heights (SBHs). Simulations carried out using calibrated parameters show better drive current (≈ 10− 2 − 3A/μ m) compared to quantum tunneling simulated state-of-the-art devices 4 5A/μ m). addition, butterfly curves symmetric high (NMH) low (NML) noise margins 0.43V 0.29V zero finite SBHs, respectively. switching is shown have an overshoot 0.15 V realistic SBHs which then eliminated case SBHs. last section, it also demonstrated simplified Nickel (NiSi) does not hamper device.