Device modeling of oxide–semiconductor channel antiferroelectric FETs using half-loop hysteresis for memory operation

Abstract In this work, the memory characteristics of oxide–semiconductor (OS) channel antiferroelectric FETs (AFeFETs) are investigated by developing a compact model AFeFETs. The consists an analytic junctionless FeFET and newly developed AFe Preisach model. can reproduce arbitrary minor loop measurement results. key feature AFeFETs is using half-loop hysteresis in contrast to full Fe. Only small net charge required minority carrier generation not necessary for erase operation, which preferable typical OS channel. Based on model, we systematically vary device parameters gate insulator, analyze window operation point analysis, show potential applications.