Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in form of a sheet. The mNS-FET has superior for stacked channels; consequently, it can significantly reduce short-channel effect (SCE); however, punch-through inevitably occurs bottom portion that is not surrounded by gates, resulting large leakage current. Moreover, as size semiconductor decreases several nanometers, influence parasitic resistance and capacitance increases. Therefore, essential apply design–technology co-optimization, which analyzes only characteristics from perspective but also performance circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation analyze directly fabricated model describes current–voltage using Berkeley insulated-gate transistor–common multi-gate (BSIM–CMG) parameters. Through model, completed Simulation Program with Integrated Circuit Emphasis (SPICE) analysis analyzed viewpoint devices circuits. When comparing according presence or absence oxide conducting above research method, confirmed subthreshold slope (SS) drain-induced barrier lowering (DIBL) are improved, power increased.