منابع مشابه
Design of Low Power Sigma Delta ADC
A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital fi...
متن کاملDesign and Implementation of a Low Power Second Order Sigma-Delta ADC
Sigma-Delta (∑-∆) analog to digital converters are well known for its use in high accuracy wireless communication applications. It is alternative for low power, high resolution (greater than 12 bits) converters, which can be ultimately integrated on digital signal Processor ICs. In this work Over Sampling concept is used to address the problem of power dissipation and noise in ADCs. In this pap...
متن کاملDesign and Simulation of Sigma Delta ADC Using VHDL AMS
There is two main parts of Sigma-delta ADC: analog modulator and digital filter, the performance of modulator determines the performance of sigma-delta ADC, so the design of modulator is very important. This paper introduces the principle of sigma-delta ADC modulator with high accuracy and the applied over sampling technique, noise shaping technique and multi-bit quantize technique. This paper ...
متن کاملBIST for discrete - time Sigma - Delta ADC
Scientific Test and diagnosis for mixed-signal/RF integrated devices, design-for-test, behavioral and statistical modeling Fields of expertise Microelectronics, control, statistics Know-how Test metrics estimation, machine-learning-based test, parameter estimation for test and control, diagnosis, mixed-signal/RF design-for-test Industrial transfer Techniques of integrated test for analog-to-dig...
متن کاملDesign of low power pipelined ADC
A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.
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ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2012
ISSN: 0976-1527
DOI: 10.5121/vlsic.2012.3407