Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature
نویسندگان
چکیده
An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software used to implement the suggested topology 16nm predictive technology model (PTM). Investigations into comparisons conventional 6T, 8T, 9T, 10T SRAM cells have been made regarding write operations' delay power consumption as well product (PDP). The simulation outcomes show that design offers fastest PDP optimization overall. Compared current 6T 9T topologies, noise margin also enhanced. Finally, comparison of figure merit (FoM) indicates best efficiency proposed design.
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ژورنال
عنوان ژورنال: International journal of electrical and computer engineering systems
سال: 2022
ISSN: ['1847-6996', '1847-7003']
DOI: https://doi.org/10.32985/ijeces.13.9.11