Design of D flip-flop and T flip-flop using Mach–Zehnder interferometers for high-speed communication
نویسندگان
چکیده
منابع مشابه
Design High Speed Conventional D Flip-Flop using 32nm CMOS Technology
A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divid...
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ژورنال
عنوان ژورنال: Applied Optics
سال: 2015
ISSN: 0003-6935,1539-4522
DOI: 10.1364/ao.54.006397