Design of an Efficient Parallel Comparator Architecture for Low Power Delay Product

A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance power analysis of various state-of-the-art designs. The main advantages design are its high speed efficiency maintained over wide range operands size, which useful at low-input data activity environments. circuit uses minimum fan-in fan-out gates achieving low dissipation. Utilizing 2-bit with (NAND-NOR), the parallel higher input by using radix multiplexer priority encoder. Further, decrease size encoder two times, general 4-bit reduce complexity. circuits optimized terms consumption delay, due load capacitance, leakages, reduced dynamic Each has own merits speed, consumption, Power-Delay Product (PDP). Its synthesis done on 180 nm as well 90 CMOS technology Cadence tool. physical layout process (GPDK process) obtained.