Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with storage layer separated using separation oxide was designed and analyzed technology computer-aided design (TCAD). The channel layers were to improve the inferior retention time of conventional 1T-DRAM, we adopted underlap structure reduce Shockley-Read-Hall recombination. addition, poly-Si, which has several advantages, including low manufacturing cost availability high-density three-dimensional (3D) arrays, is used easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, extracted performance by analyzing effect grain boundary (GB). proposed 1T-DRAM achieved sensing margin 14.10 μA/μm 251 ms at T = 358 K, even in existence GB.