Design and implementation of DA FIR filter for bio-inspired computing architecture

High Throughput Da-based Fir Filter for Fpga Implementation

In this paper, we present the design optimization of oneand two-dimensional fully-pipelined computing structures for areadelay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the look-up-tab...

Low-Complexity Design of FIR Filter Implementation

this paper presents a programmable digital finite impulse response (FIR) filter for low-power applications. A 10tap programmable FIR filter was implemented and fabricated in CMOS 0.25m technology based on the proposed architectural and circuit-level techniques. The chip‟s core contains approximately 130 K transistors and occupies 9.93 mm2 areas. The architecture is based on a computation sharin...

Architectures and design methodologies for bio-inspired computing machines

Design and implementation of DDA architecture for FIR Filters

Traditionally, direct implementation of a K-tap FIR filter requires K multiply-and-accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity and resource usage. To resolve this issue, we first present DA, which is a architecture without multiplier. This paper implements the DA architecture. This architecture is applicable to only one type of filter Coefficients i...

Power-efficient FIR filter architecture design for wireless embedded system

This paper presents a novel approach for implementing power-efficient finite-impulse response (FIR) filters that requires less power consumption than traditional FIR filter implementation in wireless embedded systems. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, bal...