Delay-based clock generator with edge transmission and reset
نویسندگان
چکیده
منابع مشابه
Clock aligner based on delay locked loop with double edge synchronization
In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the pand n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2014
ISSN: 1349-2543
DOI: 10.1587/elex.11.20140573